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<p>This typedef contains audio stream specific data structure.  
 <a href="struct_x_v___hdmi_rx1___frl.html#details">More...</a></p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a0eb1fb5490f5c6416d49455599444083"><td class="memItemLeft" align="right" valign="top">XV_HdmiRx1_FrlTrainingState&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0eb1fb5490f5c6416d49455599444083">TrainingState</a></td></tr>
<tr class="memdesc:a0eb1fb5490f5c6416d49455599444083"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fixed Rate Link State.  <a href="#a0eb1fb5490f5c6416d49455599444083">More...</a><br/></td></tr>
<tr class="separator:a0eb1fb5490f5c6416d49455599444083"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a84aedb9b7aa201a737728818d6349a55"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#a84aedb9b7aa201a737728818d6349a55">TimerCnt</a></td></tr>
<tr class="memdesc:a84aedb9b7aa201a737728818d6349a55"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Timer.  <a href="#a84aedb9b7aa201a737728818d6349a55">More...</a><br/></td></tr>
<tr class="separator:a84aedb9b7aa201a737728818d6349a55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa021105f3952e9e9736f572d7eaf2639"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#aa021105f3952e9e9736f572d7eaf2639">LineRate</a></td></tr>
<tr class="memdesc:aa021105f3952e9e9736f572d7eaf2639"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current Line Rate from FRL rate.  <a href="#aa021105f3952e9e9736f572d7eaf2639">More...</a><br/></td></tr>
<tr class="separator:aa021105f3952e9e9736f572d7eaf2639"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af43d413c9a668400e3c0b8fbac302e19"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#af43d413c9a668400e3c0b8fbac302e19">CurFrlRate</a></td></tr>
<tr class="memdesc:af43d413c9a668400e3c0b8fbac302e19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current FRL Rate supported.  <a href="#af43d413c9a668400e3c0b8fbac302e19">More...</a><br/></td></tr>
<tr class="separator:af43d413c9a668400e3c0b8fbac302e19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5e7fe7b2df2ad8498ac0605f9c8de79b"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#a5e7fe7b2df2ad8498ac0605f9c8de79b">Lanes</a></td></tr>
<tr class="memdesc:a5e7fe7b2df2ad8498ac0605f9c8de79b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current number of lanes used.  <a href="#a5e7fe7b2df2ad8498ac0605f9c8de79b">More...</a><br/></td></tr>
<tr class="separator:a5e7fe7b2df2ad8498ac0605f9c8de79b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2590b69cbb7cef7c8752f1ff553ab021"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#a2590b69cbb7cef7c8752f1ff553ab021">FfeLevels</a></td></tr>
<tr class="memdesc:a2590b69cbb7cef7c8752f1ff553ab021"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Supported FFE Levels for the current FRL Rate.  <a href="#a2590b69cbb7cef7c8752f1ff553ab021">More...</a><br/></td></tr>
<tr class="separator:a2590b69cbb7cef7c8752f1ff553ab021"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52827fe0fcf8a35db1def1910fada68d"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#a52827fe0fcf8a35db1def1910fada68d">FfeSuppFlag</a></td></tr>
<tr class="memdesc:a52827fe0fcf8a35db1def1910fada68d"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX Core's support of FFE Levels.  <a href="#a52827fe0fcf8a35db1def1910fada68d">More...</a><br/></td></tr>
<tr class="separator:a52827fe0fcf8a35db1def1910fada68d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a21a4013614c2eae5fd14968ad790c669"><td class="memItemLeft" align="right" valign="top">XV_HdmiRx1_FrlLtp&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#a21a4013614c2eae5fd14968ad790c669">Ltp</a></td></tr>
<tr class="memdesc:a21a4013614c2eae5fd14968ad790c669"><td class="mdescLeft">&#160;</td><td class="mdescRight">LTP to be detected by the RX core and queried by source.  <a href="#a21a4013614c2eae5fd14968ad790c669">More...</a><br/></td></tr>
<tr class="separator:a21a4013614c2eae5fd14968ad790c669"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f554039b7fe90c629cb245a727540b7"><td class="memItemLeft" align="right" valign="top">XV_HdmiRx1_FrlLtp&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0f554039b7fe90c629cb245a727540b7">DefaultLtp</a></td></tr>
<tr class="memdesc:a0f554039b7fe90c629cb245a727540b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">LTP which will be used by RX core for link training.  <a href="#a0f554039b7fe90c629cb245a727540b7">More...</a><br/></td></tr>
<tr class="separator:a0f554039b7fe90c629cb245a727540b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adfec659bf51feb8c059deb56ebf1f492"><td class="memItemLeft" align="right" valign="top">XV_HdmiRx1_FrlFfeAdjType&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___frl.html#adfec659bf51feb8c059deb56ebf1f492">LaneFfeAdjReq</a></td></tr>
<tr class="memdesc:adfec659bf51feb8c059deb56ebf1f492"><td class="mdescLeft">&#160;</td><td class="mdescRight">The RxFFE for each of the lanes.  <a href="#adfec659bf51feb8c059deb56ebf1f492">More...</a><br/></td></tr>
<tr class="separator:adfec659bf51feb8c059deb56ebf1f492"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>This typedef contains audio stream specific data structure. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="af43d413c9a668400e3c0b8fbac302e19"></a>
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          <td class="memname">u32 XV_HdmiRx1_Frl::CurFrlRate</td>
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<p>Current FRL Rate supported. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#ad8f801766bca274f8235adde45ddc085">XV_HdmiRx1_ConfigFrlLtpDetection()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a580b1f726297a49e552e2e90aa7a80f4">XV_HdmiRx1_RetrieveFrlRateLanes()</a>.</p>

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          <td class="memname">XV_HdmiRx1_FrlLtp XV_HdmiRx1_Frl::DefaultLtp</td>
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<p>LTP which will be used by RX core for link training. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#ad8f801766bca274f8235adde45ddc085">XV_HdmiRx1_ConfigFrlLtpDetection()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a07be19e39e2a3e90ea9ac937f6adfc58">XV_HdmiRx1_FrlLinkRetrain()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a8b8df1df4274fd34afc6ad600c4d1605">XV_HdmiRx1_FrlModeEnable()</a>.</p>

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<a class="anchor" id="a2590b69cbb7cef7c8752f1ff553ab021"></a>
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          <td class="memname">u8 XV_HdmiRx1_Frl::FfeLevels</td>
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<p>Number of Supported FFE Levels for the current FRL Rate. </p>

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<a class="anchor" id="a52827fe0fcf8a35db1def1910fada68d"></a>
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          <td class="memname">u8 XV_HdmiRx1_Frl::FfeSuppFlag</td>
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<p>RX Core's support of FFE Levels. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a8b8df1df4274fd34afc6ad600c4d1605">XV_HdmiRx1_FrlModeEnable()</a>.</p>

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<a class="anchor" id="adfec659bf51feb8c059deb56ebf1f492"></a>
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          <td class="memname">XV_HdmiRx1_FrlFfeAdjType XV_HdmiRx1_Frl::LaneFfeAdjReq</td>
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<p>The RxFFE for each of the lanes. </p>

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          <td class="memname">u8 XV_HdmiRx1_Frl::Lanes</td>
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<p>Current number of lanes used. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#adebf854f66fb92c37366faab549dd4a8">XV_HdmiRx1_PhyResetPoll()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a580b1f726297a49e552e2e90aa7a80f4">XV_HdmiRx1_RetrieveFrlRateLanes()</a>.</p>

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          <td class="memname">u8 XV_HdmiRx1_Frl::LineRate</td>
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<p>Current Line Rate from FRL rate. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a580b1f726297a49e552e2e90aa7a80f4">XV_HdmiRx1_RetrieveFrlRateLanes()</a>.</p>

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          <td class="memname">XV_HdmiRx1_FrlLtp XV_HdmiRx1_Frl::Ltp</td>
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<p>LTP to be detected by the RX core and queried by source. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#ad8f801766bca274f8235adde45ddc085">XV_HdmiRx1_ConfigFrlLtpDetection()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a07be19e39e2a3e90ea9ac937f6adfc58">XV_HdmiRx1_FrlLinkRetrain()</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_Frl::TimerCnt</td>
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<p>FRL Timer. </p>

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          <td class="memname">XV_HdmiRx1_FrlTrainingState XV_HdmiRx1_Frl::TrainingState</td>
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<p>Fixed Rate Link State. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#af7fd5d8f18778311dec6be080788f6f2">XV_HdmiRx1_Clear()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#ad8f801766bca274f8235adde45ddc085">XV_HdmiRx1_ConfigFrlLtpDetection()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#adaa4205184958f79b8aa3d2e39b97661">XV_HdmiRx1_ExecFrlState()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a07be19e39e2a3e90ea9ac937f6adfc58">XV_HdmiRx1_FrlLinkRetrain()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a8b8df1df4274fd34afc6ad600c4d1605">XV_HdmiRx1_FrlModeEnable()</a>.</p>

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